Non-volatile semiconductor memory device

ABSTRACT

A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims the benefit of priority from theprior Japanese Patent Application No. 2003-419379, filed on Dec. 17,2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an electrically rewritable and non-volatilesemiconductor memory device (EEPROM).

2. Description of Related Art

An EEPROM flash memory is usually formed to have an erase unit largerthan read or write unit, and this may cause the occupied area ofdecoders to be lessened. For example, a NAND-type flash memory has NANDcell units arranged therein, which constitute a cell array, each NANDcell unit having plural memory cell connected in series. Data erase isperformed by a block which is defined as a set of NAND cell unitsarranged along a word line, while data read or write is performed by apage which is defined as a set of memory cells arranged along a wordline.

The NAND-type flash memory is made to have a small unit cell sizebecause plural memory cells which constitute a NAND cell unit areconnected in series in such a manner that adjacent two memory cellsshare a source/drain diffusion layer. Further, the NAND-type flashmemory device has a page buffer, which is possible to store read data orwrite data of one page (e.g., 512 Byte), and data input/output betweenthe page buffer and I/O ports are serially transferred by a byte. Basedon these features, the NAND-type flash memory shows a high performancewhen it is applied to, for example, electric cards for storing a largecapacitive data such as image, animation, and music data.

To over-write data into a block, a block erase operation isautomatically performed prior to the data write, following it data writeis performed in the flash memory chip. To hold the data in the block tobe over-written without erasing, it is required to perform a copy-writeoperation for transferring the data to one of other blocks (i.e., spareblock) (refer to, for example, Unexamined Japanese Patent ApplicationPublication No. 2003-233992).

It is usually a host device disposed outside of the flash memory chipthat performs such a spare block management in the flash memory chip.However, the flash memory management data in the host device is notalways identical with the internal state of the flash memory. Forexample, it may be happened an event that although the block erase hasstarted in the flash memory in response to an instruction of the hostdevice, the power supply is cut off, or the flash memory is drawn outfrom the system before completion of data erase. In this case, it willbe happened a situation where in spite of that a block is designated asa spare block in the management information of the host device, it hasnot been erased in practice. To deal with this situation, it will berequired to confirm that a spare block has been erased in practice priorto use it.

Therefore, it is necessary for the host device to send erase command andaddress to a flash memory prior to using a spare block therein forexecuting spare block erase. Such the erase sequence usually includes apre-write or pre-program operation for reducing erase stress influenceson the block prior to the block erase operation. If it is alwaysrequired to adapt such the erase sequence to a spare block, which issupposed as having been erased, as it is, it will take a great timeloss.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided asemiconductor memory device including:

a cell array with electrically rewritable and non-volatile memory cellsarranged therein;

a sense amplifier circuit configured to read data of and write data intothe cell array; and

a controller configured to control read, write and erase of the cellarray, wherein

the controller executes an erase sequence for erasing a selected blockin the cell array in response to erase command and address input in sucha way of: executing a first erase-verify operation for verifying anerase state of the selected block; ending the erase sequence if theerase state of the selected block has been verified by the firsterase-verify operation; whereas executing an erase operation for theselected block if the erase state has not been verified.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a flash memory in accordance with anembodiment of the present invention.

FIG. 2 shows a cell array arrangement of the flash memory.

FIG. 3 shows a configuration of a page buffer of the flash memory.

FIG. 4 shows data threshold distributions of the flash memory.

FIG. 5 shows an erase operation flow of the flash memory.

FIG. 6 shows a bias condition at a verify-read time of the flash memory.

FIG. 7 shows a bias condition at an erase time of the flash memory.

FIG. 8 shows operation waveforms of the erase-verify operation by givingattention to the sense amplifier circuit of the flash memory.

FIG. 9 shows bias conditions at two verify-read times in accordance withanother embodiment.

FIG. 10 shows a waveform for explaining the data sense conditions at twoverify-read times in accordance with another embodiment.

FIG. 11 shows a bias condition at a read time of a NOR-type flashmemory.

FIG. 12 shows a bias condition at a write time of the NOR-type flashmemory.

FIG. 13 shows a bias condition at an erase time of the NOR-type flashmemory.

FIG. 14 shows an erase operation flow in am embodiment in which thisinvention is adapted to the NOR-type flash memory.

FIG. 15 shows another embodiment applied to a digital still camera.

FIG. 16 shows the internal configuration of the digital still camera.

FIGS. 17A to 17J show other electric devices to which the embodiment isapplied.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Illustrative embodiments of this invention will be explained withreference to the accompanying drawings below.

[Embodiment 1]

FIG. 1 shows a functional block diagram of a NAND-type flash memory inaccordance with an embodiment. A cell array 1 is, as described later,formed of NAND cell units arranged therein. A sense amplifier circuit 2,which serves as a page buffer, has sense amplifiers necessary forsensing one page read data and for holding one page write data, and acolumn gate circuit for serially transferring one page data. A rowdecoder 3 includes a word line driver and serves for selectively driveword lines of the cell array 1. Data transferring between the senseamplifier circuit 2 and external I/O terminals is done via I/O buffer 4.

To control write and erase sequences and a read operation in response toexternal control signals, a controller 5 is prepared. The controller 5serves for receiving address “Add” and command “CMD” supplied from I/Oterminals, to transmit the address to the row decoder 3 and page buffer2, and perform operation controls instructed by the command. A highvoltage generating circuit 6 generates various boosted voltagesnecessary for read, write and erase modes under the control of thecontroller 5.

FIG. 2 shows a detailed arrangement of the cell array 1. A plurality ofmemory cells (e.g., sixteen cells in this case) MC0–MC15 are connectedin series to constitute a NAND cell unit NU. These plural NAND cellunits are arranged in a matrix manner. Each memory cell MCi is astacked-gate transistor, which has a data storage layer formed of, forexample, a floating gate, and stores a threshold voltage as a data in anon-volatile manner, which is defined by a charge storage state. Thecell data is electrically rewritable by electron injection into thefloating gate and releasing the stored charge.

One end of the NAND cell unit NU is coupled to a bit line BL via aselect gate transistor SG1, and the other end to a common source lineCELSRC via another select gate transistor SG2. Control gates of thememory cells in a NAND cell unit NU are coupled to different word linesWLi. Gates of the select gate transistors SG1 and SG2 are coupled toselect gate lines SGD and SGS, respectively, which are disposed inparallel with the word lines WLi.

One page, which is defined as a set of memory cells arranged along aword line, serves as a unit of data read and write. A set of NAND cellunits share word lines, which is defined as a block, serves as a unit ofdata erase. Usually, a plurality of blocks BLKj (j=0, 1, . . . ) arearranged in the direction of the bit line BL.

FIG. 3 shows a configuration of a sense amp unit in the page buffer 2.An NMOS transistor MN1 disposed between a sense node Nsen and a bit lineBL serves for clamping the bit line precharged voltage and as apre-sense for amplifying bit line voltage. Further, to the sense nodeNsen, a precharging NMOS transistor MN2 is coupled, and if necessary acapacitor C is coupled.

The sense node Nsen is connected to a data node N1 of a dada latch 21via a transferring NMOS transistor MN3. The data latch 21 is formed ofclocked inverters CI1 and CI2 connected in parallel and in the reverseddirection between data node N1 and N2.

Disposed between the sense node Nsen and data node N1 is a write-backcircuit 22, which stores write data in each write cycle to write back inaccordance with each verify-read result. The gate of an NMOS transistorMN4, drain of which is connected to a power supply node Vdd, serves as adata storage node NR. Between this storage node NR and the data node N1,a data transferring NMOS transistor MN5 is disposed. To write back data,Vdd or Vss, to the sense node in accordance with the data stored at thenode NR, an NMOS transistor MN6 is disposed between the NMOS transistorMN4 and the sense node Nsen.

Connected to the data node N2 is a verify-check circuit 23. Thisverify-check circuit 23 is to check whether write of erase has beencompleted or not by use of a check signal CHK after verify-reading inthe write-verify or erase-verify. With respect to the erase-verify, theverify-check circuit 23 detects whether the data node N2 in the senseamplifier has become “H” or not. In other words, the verify-checkcircuit 23 is configured to determine the potential of the common signalline COM based on an AND logic of the entire data nodes N2 of all senseamplifiers. The controller 5 monitors this signal line COM to judgewhether the verify result is “Pass” or “Fail”.

FIG. 4 shows data threshold voltage distributions in case the NAND flashmemory device in accordance with this embodiment is used to store binarydata. The negative threshold voltage state is defined as data “1” (erasestate), and the positive threshold state as data “0” (write state in anarrow sense). Data “0” write is defined as an operation, in whichelectrons are injected into the floating gate of a selected memory cellfrom channel thereof by FN tunneling.

In detail, one page data write is done with the steps of: transferringVss and Vdd−Vth (Vth is threshold voltage of the select gate transistor)to the selected cell's channels of the NAND cell units from the bitlines in correspondence with write data “0” and “1”; and applying awrite voltage Vpgm (for example, Vpgm=20V) to a selected word line. In amemory cell or cells applied with “0” data, a large electric field isapplied between the floating gate and the cell channel, electrons areinjected into the floating gate (i.e., “0” write). In contrast to this,in a memory cell or cells applied with “1” data, the channel will beboosted in potential by capacitive coupling, resulting in that electroninjection into the floating gate does not occur (i.e., write inhibited).

Data write is performed, in practice, by repeating write voltageapplication and verify-read for verifying the write state (i.e., writeverify) until the entire write data of one page are completely written.

In this embodiment, it is adapted an erase sequence including aconfirmation operation for confirming that an erase block has beensurely erased, which is recognized as a spare block by a host device.FIG. 5 shows a flow chart of an erase sequence in accordance with thisembodiment.

Receiving erase command and address supplied from a host device, theflash memory initializes the row/column addresses (at step S1), and thenexecutes erase-verify for a selected block selected by the addresssupplied from the host device (at step S2). The bias condition used atthe erase-verify is, for example, shown in FIG. 6, which shows only oneNAND cell unit. 0V is applied to the entire word lines WLi; a passvoltage Vread to the select gate lines SGD and SGS; and Vss to thecommon source line CELSRC. The bit line BL is precharged at a certainvoltage VBL (<Vdd).

With this voltage application, in case the entire memory cells in a NANDcell unit are in erase states with negative threshold voltages, thesememory cells become on, and flow channel currents, thereby dischargingthe corresponding bit line BL. If there is any un-erased memory cell(i.e., “0” data cell), the NAND cell unit does not become conductive,thereby retaining the bit line to be at about the precharged voltage VBLeven though it flows a small leakage current. Therefore, detect whetherthe respective bit lines BL are discharged or not, and it may be judgedwhether the respective NAND cell units have been erased or not. Inpractice, the verify judgment is done by detecting whether the entiredata nodes N2 have become “H” or not in the entire sense amplifiers as aresult of the verify-read.

Outputting a “Pass” flag in case the block erase has been confirmed inthe erase-verify judgment step S2, the flash memory ends the erasesequence without proceeding to the practical erase cycles. If it hasbeen judged “Fail” in the erase-verify judgment, the erase cycles willbe performed after a preliminary write operation is executed for theselected block prior to the erase operation in order to reduce erasestress influences on the selected block. In detail, the preliminarywrite (i.e., pre-write) operations are repeated with the steps of:initializing row/column addresses (at step S3); performing pre-write forthe head page (at step S5); incrementing the page address (at step S6);and performing pre-write for the next page. Although it is shown anexample that verify-read (i.e., write-verify) is not performed in thepreliminary write cycles, it should be appreciated that write-verify maybe adaptable to the preliminary write cycles. If having been confirmedthat write completion (AEND=“H”) is confirmed from the head page to thelast page in the step S4, proceed to erase cycles.

The erase cycles are performed with the steps of: initializingrow/column addresses (at step S7); and performing erase-verify for theselected block again (at step S8). The erase-verify is basically thesame as that in the step S2. If the verify judgment results in “Fail”,erase operation is performed for the selected block (at step S9), andthen the erase-verify is performed again (at step S8).

The bias condition of the erase operation is, for example, as shown inFIG. 7. 0V is applied to the entire word lines in the selected block;the select gate lines SGD, SGS, bit lines BL and common source lineCELSRC are set in a floating state; A erase voltage Vera (for example,Vera=20V) is applied to a node CPWELL of the p-type well on which thecell array is formed. With this voltage application, electrons stored inthe floating gates of the entire memory cells in the selected block willbe released to the cell channels. If the erase verify judgment resultsin “Pass”, end the above-described erase operation.

FIG. 8 shows a timing chart of the erase-verify read operation in thesteps S2 and S8 taking notice to the sense unit shown in FIG. 3. Attiming t0, VBL+Vth (Vth is threshold voltage of NMOS transistor) isapplied to the gate node BLCLAMP to turn on the clamping transistor MN1,and Vdd+Vth is applied to the gate node PRE of the prechargingtransistor MN2 simultaneously. VBL is a voltage lower than the powersupply voltage of Vdd. With this voltage application, the bit line BL isprecharged at VBL; and the sense node Nsen is to Vdd.

Turn off the clamping transistor MN1, and disable the data latch 21 byletting the sense amplifier activation signals, SEN and LAT, beSEN=LAT=“L” at timing t1. Thereafter, turn off the prechargingtransistor MN2, and apply a “H” level voltage, Vread, to the select gateline SGD located on the bit line side in the selected block at timingt2. The select gate line SGS located on the common source line CELSRCside has been previously applied with the “H” level voltage, and theentire word lines WL also has been previously applied with 0V. Under thevoltage application condition, the bit line BL will be discharged inaccordance with data. That is, if the entire memory cells in a NAND cellunit have been erased, the corresponding bit line BL is discharged (asshown by a dotted line). In case there is any memory cell, which has notbeen erased, the corresponding bit line BL is not discharged (as shownby a solid line). Although FIG. 8 shows typical two discharge curves,one being a case where the bit line is discharged; and the other a casewhere the bit line is not discharged, various bit line discharge curveswill be obtained in practice as being different for the respective bitlines from each other in accordance with cells' data threshold voltagesin the NAND cell unit.

After a certain waiting time, apply a “H” level to the gate node BLC toturn on the transferring transistor MN3 at timing t3, and apply asense-use voltage Vsen+Vth to the gate BLCLAMP of the clampingtransistor MN1 at timing t4. Vsen is set at a voltage value between “H”level (un-erased) and “L” level (erased) of the bit line at this timing.

In case the entire memory cells in a NAND cell unit have been erased,therefore the bit line voltage has been reduced in potential, theclamping transistor MN1 turns on with the above-described voltageapplication, whereby the charge of the sense node Nsen and data node N1is transferred toward the bit line BL. Since the bit line BL has usuallya capacitance sufficiently larger than those of the sense node Nsen anddata node N1, the sense node Nsen and data node N1 will be reduced to beapproximately equal to the bit line voltage level due to theabove-described charge distribution. In case the bit line has not beendischarged, the clamp transistor MN1 is kept off. Therefore, the sensenode Nsen and data node N1 are held at the “H” level.

After having turned off the clamping transistor MN1, let the activationsignals SEN and LAT be “H” at timing T5 and T6, respectively. As aresult, in case the entire memory cells have been erased, a data stateof: N1=“L” (=Vss); N2=“H”(=Vdd) will be lathed, whereas in case there isan un-erased memory cell(s), a reverse data will be latched. Asdescribed above, the verify judgment becomes “Pass” when the data nodesN1 of the entire sense amplifiers are detected to be “H” with the verifycheck circuit 23.

According to this embodiment described above, the flash memory executeserase-verify for a selected block in the beginning when receiving anerase command, and ends the erase sequence of the selected block withoutexecuting pre-write and erase in case it is in an erase state.Therefore, a host device is allowed to issue an erase command for aspare block without checking whether the spare block has been erased ornot. As a result, it is possible to avoid a waste of long time that istaken for executing read and erase cycles. Especially, in the NAND-typeflash memory, the erase-verify read may be performed by a block in ashort time as different from the ordinary read so that this inventionhas a large merit.

Although, it has been explained, in the above-described embodiment, anerase verify scheme of detecting whether the precharged bit line isdischarged or not (or the discharge degree), it is possible to useanther scheme of detecting whether the bit line is charged or not (orthe charge degree). In the latter scheme, bit line BL is precharged at0V, and under the bias condition of: 0V is applied to the entire wordlines WL; Vdd to the common source line CELSRC; and pass voltage Vreadto the select gate lines SGD and SGS, a cell current is carried from thecommon source line CELSRC to the bit line BL. If a NAND cell unit hasbeen erased in a state where the upper limit of threshold voltages ofthe entire memory cells therein is lower than Vt (negative), the bitline will be charged up to |Vt|. By contrast, if there is an un-erasedcell, threshold voltage of which is higher than 0V, in the NAND cellunit, no cell current flow, and the bit line BL is held at 0V. Bydetecting such the bit line charge state, erase-verify may be performed.

[Embodiment 2]

In the operation flow shown in FIG. 5 in the above-described embodiment,the erase-verify operations at steps S2 and S8 are performed with thesame verify judgment condition. However, even if the threshold voltagesof erased cells have a large and negative value just after havingerased, those are changed in the positive direction due to stressesinfluenced on un-selected memory cells in data read and write modesafter erasure. Further, it may be generated a case where the initialerase-verify step S2 is passed, but the second erase-verify step S8 isnot passed due to variations of temperature and voltage conditions.Therefore, it is useful that the verify judgment conditions (i.e.,verify-read conditions) are set to be different from each other betweentwo steps S2 and S8.

One approach, for the purpose of this, is to set the bias conditions ofthe memory cells in the erase-verify mode to be different from eachother. For example, FIG. 9 shows an example where word lines are appliedwith 0.5V at the first verify step S2, while they are applied with 0V atthe second verify step S8. That is, the verify-read condition at thefirst verify step is more eased or lightened than that of the secondverify step.

Another approach is to set the data sense timings of the verify-readmodes to be different from each other. As shown in FIG. 10, data sensingmargins of “0” (not erased) and “1” (erased) at the verify time aredetermined based on the bit line discharge time, which is defined as atime length from t2 to t4 (t4 a or t4 b). Therefore, make the datasensing timings t4 different between the two erase-verify steps S2 andS8, and these verify-read conditions become different from each other.

It is also useful, as a third approach, to set the sensibility of thesense amplifier in the first erase-verify step S2 to be different fromthat in the second erase-verify step S8. In detail, the sense-usevoltages Vsen, which is applied to the gate of the clamping transistorMN1, are made different between two verify steps S2 and S8. This makes,as easily understood from FIG. 10, the verify-read conditions differentfrom each between the two steps.

[Embodiment 3]

The flash memory in the embodiment 1 is designed to execute a series ofsequences as shown in FIG. 5 in response to an erase command. Bycontrast to this, it is possible to prepare a command, which is usedonly for an erase-verify operation, independently of the erase command,thereby making the erase-verify step S2 shown in FIG. 5 independent ofthe erase sequence. In this case, it is designed preferably to output a“Pass/Fail” flag of the erase-verify outside of the chip. In accordancewith this flag, it becomes possible to select that following block eraseoperation is to be executed or not.

[Embodiment 4]

A NAND-type flash memory has a feature that power consumption in theerase mode is little because data erase thereof is performed with an FNtunneling current. Due to this, it is easily possible to erase aplurality of blocks simultaneously. Therefore, this invention iseffective in a case where plural blocks are simultaneously erased. Itshould be noted in this case that erase-verify is to be performed by ablock.

[Embodiment 5]

Although it has been explained for a NAND-type flash memory in theabove-described embodiments, this invention may be adapted to NOR-typeflash memories. FIGS. 11 to 13 show bias relationships in the memorycell array in various operation modes of a NOR-type flash memory device.

At a read time, as shown in FIG. 11, a selected word line WL0 is appliedwith 5V; unselected word line WL1 and source line SL are applied with0V; and bit lines BL are applied with 1V. With this voltage application,plural memory cells disposed along the selected word line WL0 (i.e., onepage cells) may be read.

At a write time, as shown in FIG. 12, 10V is applied to a selected wordline WL0; 0V is applied to unselected word line WL1 and source line SL;and 5V and 0V are applied to bit lines BL in accordance with write data.With this voltage application, a large channel current flows in memorycell(s), to which 5V is applied from the bit line BOL, in the entirememory cells disposed along the selected word line WL0, and electronsare generated by impact ionization to be injected into floating gate(s)thereof.

Erasure may be performed by a block. As shown in FIG. 13, bit lines areset in a floating state; word lines in a selected block are applied with−10V; and source line SL is applied with 10V. With this voltageapplication, the entire memory cells in the selected block releaseelectrons stored in floating gates thereof to source diffusion layersside. That is, the entire memory cells may be erased.

In the NOR-type flash memory, read operations in write-verify anderase-verify are basically performed by a page as similar to that shownin FIG. 11. That is, it is impossible in the NOR-type flash memory toperform erase-verify with a read operation for verifying an erase stateof a block unlike NAND-type flash memory. Therefore, although theembodiments 1–4 may be basically adapted to the NOR-type flash memory,it is required of, for example, the erase-verify step S2 shown in FIG. 5to be repeated for plural pages in the block.

In detail, FIG. 14 shows an operation flow to which the erase-sequenceas similar to the embodiment 1 is adapted to the NOR-type flash memory.The flash memory receives an erase command supplied from a host device,and then initializes row/column addresses (at step S11). Following it,the flash memory executes erase-verify for a selected block, which isselected by an address signal supplied from the host device (at stepS13). If the erase-verify results in “Pass”, count up the address (atstep S14), and judge whether it has been proceeded to the final address(AEND=“H”) or not (at step S12). These erase-verify operations will berepeatedly performed page by page. If the erase-verify operation hasreached the final address without outputting “Fail”, this designatesthat the block erase has been verified. In this case, the flash memoryoutputs a “Pass” flag outside of the chip, and ends the erase operationflow without proceeding to practical erase cycles.

If it has been judged “Fail” in the erase-verify judgment, the erasecycles will be performed after a preliminary write operation is executedfor the selected block prior to the erase operation in order to reduceerase stress influences on the selected block. In detail, thepreliminary write (i.e., pre-write) operations are repeated with thesteps of: initializing row/column addresses (at step S15); performingpre-write for the head page (at step S17); incrementing the page address(at step S18); and performing pre-write for the next page. Although itis shown an example that verify-read (i.e., write-verify) is notperformed in the preliminary write cycles, it should be appreciated thatwrite-verify may be adaptable to the preliminary write cycles. If havingbeen confirmed that write completion (AEND=“H”) is confirmed from thehead page to the last page in the step S16, proceed to erase cycles.

The erase cycles are performed with the steps of: initializingrow/column addresses (at step S19); and performing erase-verify for theselected block again. The erase-verify steps S20–S23 are performed by apage as basically similar to those in the step S12–S14. If the verifyjudgment results in “Fail”, erase operation is performed for theselected block at a time (at step S22), and then the erase-verify isperformed again (at step S21). The erase-verify having reaches the finalpage, the above-described erase operation ends.

[Embodiment 6]

As an embodiment, an electric card using the non-volatile semiconductormemory devices according to the above-described embodiments 1–5 of thepresent invention and an electric device using the card will bedescribed bellow.

FIG. 15 shows an electric card according to this embodiment and anarrangement of an electric device using this card. This electric deviceis a digital still camera 101 as an example of portable electricdevices. The electric card is a memory card 61 used as a recordingmedium of the digital still camera 101. The memory card 61 incorporatesan IC package PK1 in which the non-volatile semiconductor memory deviceor the memory system according to the above-described embodiments isintegrated or encapsulated.

The case of the digital still camera 101 accommodates a card slot 102and a circuit board (not shown) connected to this card slot 102. Thememory card 61 is detachably inserted in the card slot 102 of thedigital still camera 101. When inserted in the slot 102, the memory card61 is electrically connected to electric circuits of the circuit board.

If this electric card is a non-contact type IC card, it is electricallyconnected to the electric circuits on the circuit board by radio signalswhen inserted in or approached to the card slot 102.

FIG. 16 shows a basic arrangement of the digital still camera. Lightfrom an object is converged by a lens 103 and input to an image pickupdevice 104. The image pickup device 104 is, for example, a CMOS sensorand photoelectrically converts the input light to output, for example,an analog signal. This analog signal is amplified by an analog amplifier(AMP), and converted into a digital signal by an A/D converter (A/D).The converted signal is input to a camera signal processing circuit 105where the signal is subjected to automatic exposure control (AE),automatic white balance control (AWB), color separation, and the like,and converted into a luminance signal and color difference signals.

To monitor the image, the output signal from the camera processingcircuit 105 is input to a video signal processing circuit 106 andconverted into a video signal. The system of the video signal is, e.g.,NTSC (National Television System Committee). The video signal is inputto a display 108 attached to the digital still camera 101 via a displaysignal processing circuit 107. The display 108 is, e.g., a liquidcrystal monitor.

The video signal is supplied to a video output terminal 110 via a videodriver 109. An image picked up by the digital still camera 101 can beoutput to an image apparatus such as a television set via the videooutput terminal 110. This allows the pickup image to be displayed on animage apparatus other than the display 108. A microcomputer 111 controlsthe image pickup device 104, analog amplifier (AMP), A/D converter(A/D), and camera signal processing circuit 105.

To capture an image, an operator presses an operation button such as ashutter button 112. In response to this, the microcomputer 111 controlsa memory controller 113 to write the output signal from the camerasignal processing circuit 105 into a video memory 114 as a flame image.The flame image written in the video memory 114 is compressed on thebasis of a predetermined compression format by a compressing/stretchingcircuit 115. The compressed image is recorded, via a card interface 116,on the memory card 61 inserted in the card slot.

To reproduce a recorded image, an image recorded on the memory card 61is read out via the card interface 116, stretched by thecompressing/stretching circuit 115, and written into the video memory114. The written image is input to the video signal processing circuit106 and displayed on the display 108 or another image apparatus in thesame manner as when image is monitored.

In this arrangement, mounted on the circuit board 100 are the card slot102, image pickup device 104, analog amplifier (AMP), A/D converter(A/D), camera signal processing circuit 105, video signal processingcircuit 106, display signal processing circuit 107, video driver 109,microcomputer 111, memory controller 113, video memory 114,compressing/stretching circuit 115, and card interface 116.

The card slot 102 need not be mounted on the circuit board 100, and canalso be connected to the circuit board 100 by a connector cable or thelike.

A power circuit 117 is also mounted on the circuit board 100. The powercircuit 117 receives power from an external power source or battery andgenerates an internal power source voltage used inside the digital stillcamera 101. For example, a DC—DC converter can be used as the powercircuit 117. The internal power source voltage is supplied to therespective circuits described above, and to a strobe 118 and the display108.

As described above, the electric card according to this embodiment canbe used in portable electric devices such as the digital still cameraexplained above. However, the electric card can also be used in variousapparatus such as shown in FIGS. 17A to 17J, as well as in portableelectric devices. That is, the electric card can also be used in a videocamera shown in FIG. 17A, a television set shown in FIG. 17B, an audioapparatus shown in FIG. 17C, a game apparatus shown in FIG. 17D, anelectric musical instrument shown in FIG. 17E, a cell phone shown inFIG. 17F, a personal computer shown in FIG. 17G, a personal digitalassistant (PDA) shown in FIG. 17H, a voice recorder shown in FIG. 17I,and a PC card shown in FIG. 17J.

1. A non-volatile semiconductor memory device comprising: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into said cell array; and a controller configured to control read, write and erase said cell array, wherein said controller executes an erase sequence for erasing a selected block in said cell array in response to erase command and address input, the erase sequence including executing a first erase-verify operation for verifying an erase state of the selected block on receiving an erase command; executing a first erase operation of the selected block after the first erase-verify operation if the first erase-verify operation acknowledges that a previous erasing was not successful; and ending the erase sequence without executing the first erase operation if the first erase-verify operation acknowledges that the previous erasing was successful.
 2. The non-volatile semiconductor memory device according to claim 1, wherein said controller executes a preliminary write operation for the selected block prior to the erase operation in order to reduce erase stress influenced on the selected block.
 3. The non-volatile semiconductor memory device according to claim 1, wherein the erase operation of the selected block is performed by repeating a second erase-verify operation for verifying the erase state of the selected block and an erase voltage application operation for applying an erase voltage to the selected block until the erase state is verified, and wherein verify-read conditions in the first and second erase-verify operations are different from each other.
 4. The non-volatile semiconductor memory device according to claim 3, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with said sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the respective read biases to be different from each other.
 5. The non-volatile semiconductor memory device according to claim 3, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with said sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the data sense timings to be different from each other.
 6. The non-volatile semiconductor memory device according to claim 3, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with said sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the sensibility of said sense amplifier circuit in the first erase-verify operation to be different from that in the second erase-verify operation.
 7. The non-volatile semiconductor memory device according to claim 1, wherein the first erase-verify operation is executed in response to a specified command input independently of the erase sequence.
 8. The non-volatile semiconductor memory device according to claim 1, wherein said cell array has a plurality of NAND cell units arranged therein, each NAND cell unit being formed of: memory cells connected in series, control gates of which are coupled to different word lines; a first select gate transistor coupling one end of the memory cells connected in series to a bit line; and a second select gate transistor coupling the other end to a common source line, said cell array being divided into plural blocks in the bit line direction each defined as a set of NAND cell units sharing a word line.
 9. The non-volatile semiconductor memory device according to claim 8, wherein said sense amplifier circuit comprises: a clamping transistor disposed between a sense node and a bit line of said cell array for clamping a bit line voltage and for serving as a pre-sense amplifier; a precharging transistor coupled to the sense node for precharging the sense node and the bit line; and a data latch disposed for sensing bit line data and latch it, which is transferred to the sense node via the clamping transistor.
 10. The non-volatile semiconductor memory device according to claim 1, wherein said device is formed as a NOR-type of memory, and the first erase-verify operation is so performed by repeating a page erase-verify operation as to verify the erase state of the selected block.
 11. An electric card equipped with a non-volatile semiconductor memory device, said device comprising: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into said cell array; and a controller configured to control read, write and erase said cell array, wherein said controller executes an erase sequence for erasing a selected block in said cell array in response to erase command and address, the erase sequence including: executing a first erase-verify operation for verifying the erase state of the selected block on receiving an erase command; executing a first erase operation of the selected block after the first erase-verify operation if the first erase-verify operation acknowledges that a previous erasing was not successful; and ending the erase sequence without executing the first erase operation if the first erase-verify operation acknowledges that the previous erasing was successful.
 12. An electric device comprising: a card interface; a card slot connected to said card interface; and an electric card defined in claim 11 and electrically connectable to said card slot.
 13. A method of controlling an erase sequence of a non-volatile semiconductor memory device, the erase sequence being to erase a selected block in response to erase command and address input, comprising: initially executing a first erase-verify operation for verifying an erase state of the selected block on receiving an erase command; executing a first erase operation of the selected block after the first erase-verify operation if the first erase-verify operation acknowledges that a previous erasing was not successful; and ending the erase sequence without executing the first erase operation if the first erase-verify operation acknowledges that the previous erasing was successful.
 14. The method according to claim 13, further comprising: executing a preliminary write operation for the selected block prior to the erase operation in order to reduce erase stress influenced on the selected block.
 15. The method according to claim 13, wherein the erase operation of the selected block is performed by repeating a second erase-verify operation for verifying the erase state of the selected block and an erase voltage application operation for applying an erase voltage to the selected block until the erase state is verified, and wherein verify-read conditions in the first and second erase-verify operations are different from each other.
 16. The method according to claim 15, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with a sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the respective read biases to be different from each other.
 17. The method according to claim 15, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with a sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the data sense timings to be different from each other.
 18. The method according to claim 15, wherein the first and second erase-verify operations are performed by data sensing at predetermined timings with a sense amplifier circuit by applying the respective read biases to memory cells in the selected block, and wherein the verify-read conditions are made different based on setting the sensibility of said sense amplifier circuit in the first erase-verify operation to be different from that in the second erase-verify operation.
 19. The method according to claim 13, wherein the first erase-verify operation is executed independently of the erase sequence in response to a command.
 20. The method according to claim 13, wherein said device includes a cell array with a plurality of NAND cell units arranged therein, each NAND cell unit being formed of: memory cells connected in series, control gates of which are coupled to different word lines; a first select gate transistor coupling one end of the memory cells connected in series to a bit line; and a second select gate transistor coupling the other end to a common source line, said cell array being divided into plural blocks in the bit line direction each defined as a set of NAND cell units sharing a word line. 